diff -urN --exclude-from=/home/davej/.exclude linux-ac/arch/i386/kernel/bluesmoke.c linux-dj/arch/i386/kernel/bluesmoke.c
--- linux-ac/arch/i386/kernel/bluesmoke.c	Wed Aug 15 22:53:09 2001
+++ linux-dj/arch/i386/kernel/bluesmoke.c	Wed Aug 15 22:58:03 2001
@@ -19,7 +19,7 @@
 	u32 mcgstl, mcgsth;
 	int i;
 	
-	rdmsr(0x17a, mcgstl, mcgsth);
+	rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 	if(mcgstl&(1<<0))	/* Recoverable ? */
 		recover=0;
 
@@ -27,7 +27,7 @@
 	
 	for(i=0;i<banks;i++)
 	{
-		rdmsr(0x401+i*4,low, high);
+		rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high);
 		if(high&(1<<31))
 		{
 			if(high&(1<<29))
@@ -38,18 +38,18 @@
 			high&=~(1<<31);
 			if(high&(1<<27))
 			{
-				rdmsr(0x402+i*4, alow, ahigh);
+				rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
 				printk("[%08x%08x]", alow, ahigh);
 			}
 			if(high&(1<<26))
 			{
-				rdmsr(0x402+i*4, alow, ahigh);
+				rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
 				printk(" at %08x%08x", 
 					high, low);
 			}
 			printk("\n");
 			/* Clear it */
-			wrmsr(0x401+i*4, 0UL, 0UL);
+			wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
 			/* Serialize */
 			wmb();
 		}
@@ -61,7 +61,7 @@
 		panic("Unable to continue");
 	printk(KERN_EMERG "Attempting to continue.\n");
 	mcgstl&=~(1<<2);
-	wrmsr(0x17a,mcgstl, mcgsth);
+	wrmsr(MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
 }
 
 /*
@@ -71,8 +71,8 @@
 static void pentium_machine_check(struct pt_regs * regs, long error_code)
 {
 	u32 loaddr, hi, lotype;
-	rdmsr(0x0, loaddr, hi);
-	rdmsr(0x1, lotype, hi);
+	rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
+	rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
 	printk(KERN_EMERG "CPU#%d: Machine Check Exception:  0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
 	if(lotype&(1<<5))
 		printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
@@ -133,8 +133,8 @@
 		machine_check_vector = pentium_machine_check;
 		wmb();
 		/* Read registers before enabling */
-		rdmsr(0x0, l, h);
-		rdmsr(0x1, l, h);
+		rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
+		rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
 		if(done==0)
 			printk(KERN_INFO "Intel old style machine check architecture supported.\n");
 		/* Enable MCE */		
@@ -161,17 +161,17 @@
 	
 	if(done==0)
 		printk(KERN_INFO "Intel machine check architecture supported.\n");
-	rdmsr(0x179, l, h);
+	rdmsr(MSR_IA32_MCG_CAP, l, h);
 	if(l&(1<<8))
-		wrmsr(0x17b, 0xffffffff, 0xffffffff);
+		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 	banks = l&0xff;
 	for(i=1;i<banks;i++)
 	{
-		wrmsr(0x400+4*i, 0xffffffff, 0xffffffff); 
+		wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff); 
 	}
 	for(i=0;i<banks;i++)
 	{
-		wrmsr(0x401+4*i, 0x0, 0x0); 
+		wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0); 
 	}
 	set_in_cr4(X86_CR4_MCE);
 	printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", smp_processor_id());
@@ -191,10 +191,10 @@
 	/* Winchip C6 */
 	machine_check_vector = winchip_machine_check;
 	wmb();
-	rdmsr(0x107, lo, hi);
+	rdmsr(MSR_IDT_FCR1, lo, hi);
 	lo|= (1<<2);	/* Enable EIERRINT (int 18 MCE) */
 	lo&= ~(1<<4);	/* Enable MCE */
-	wrmsr(0x107, lo, hi);
+	wrmsr(MSR_IDT_FCR1, lo, hi);
 	__asm__ __volatile__ (
 		"movl %%cr4, %%eax\n\t"
 		"orl $0x40, %%eax\n\t"
diff -urN --exclude-from=/home/davej/.exclude linux-ac/arch/i386/kernel/mtrr.c linux-dj/arch/i386/kernel/mtrr.c
--- linux-ac/arch/i386/kernel/mtrr.c	Wed Aug 15 22:52:49 2001
+++ linux-dj/arch/i386/kernel/mtrr.c	Wed Aug 15 22:58:03 2001
@@ -607,7 +607,7 @@
 {
     unsigned long low, high;
 
-    rdmsr (0xC0000085, low, high);
+    rdmsr (MSR_K6_UWCCR, low, high);
     /*  Upper dword is region 1, lower is region 0  */
     if (reg == 1) low = high;
     /*  The base masks off on the right alignment  */
@@ -771,7 +771,7 @@
     /*
      *	Low is MTRR0 , High MTRR 1
      */
-    rdmsr (0xC0000085, regs[0], regs[1]);
+    rdmsr (MSR_K6_UWCCR, regs[0], regs[1]);
     /*
      *	Blank to disable
      */
@@ -793,7 +793,7 @@
      *	disable local interrupts, write back the cache, set the mtrr
      */
     __asm__ __volatile__ ("wbinvd" : : : "memory");
-    wrmsr (0xC0000085, regs[0], regs[1]);
+    wrmsr (MSR_K6_UWCCR, regs[0], regs[1]);
     if (do_safe) set_mtrr_done (&ctxt);
 }   /*  End Function amd_set_mtrr_up  */
 
@@ -826,7 +826,7 @@
     }
     centaur_mcr[reg].high = high;
     centaur_mcr[reg].low = low;
-    wrmsr (0x110 + reg, low, high);
+    wrmsr (MSR_IDT_MCR0 + reg, low, high);
     if (do_safe) set_mtrr_done( &ctxt );
 }   /*  End Function centaur_set_mtrr_up  */
 
@@ -2012,12 +2012,12 @@
      * find out what the bios might have done.
      */
      
-    rdmsr(0x120, lo, hi);
+    rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
     if(((lo>>17)&7)==1)		/* Type 1 Winchip2 MCR */
     {
     	lo&= ~0x1C0;		/* clear key */
     	lo|= 0x040;		/* set key to 1 */
-	wrmsr(0x120, lo, hi);	/* unlock MCR */
+	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);	/* unlock MCR */
     }    
     
     centaur_mcr_type = 1;
@@ -2031,7 +2031,7 @@
     	if(centaur_mcr[i]. high == 0 && centaur_mcr[i].low == 0)
     	{
     		if(!(lo & (1<<(9+i))))
-			wrmsr (0x110 + i , 0, 0);
+			wrmsr (MSR_IDT_MCR0 + i , 0, 0);
 		else
 			/*
 			 *	If the BIOS set up an MCR we cannot see it
@@ -2047,7 +2047,7 @@
      */
 
     lo |= 15;			/* Write combine enables */
-    wrmsr(0x120, lo, hi);
+    wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
 }   /*  End Function centaur_mcr1_init  */
 
 /*
@@ -2071,10 +2071,10 @@
     for (i = 0; i < 8; ++i)
     {
     	if(centaur_mcr[i]. high == 0 && centaur_mcr[i].low == 0)
-		wrmsr (0x110 + i , 0, 0);
+		wrmsr (MSR_IDT_MCR0 + i , 0, 0);
     }
 
-    wrmsr(0x120, 0x01F0001F, 0);	/* Write only */
+    wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);	/* Write only */
 }   /*  End Function centaur_mcr0_init  */
 
 /*
diff -urN --exclude-from=/home/davej/.exclude linux-ac/arch/i386/kernel/setup.c linux-dj/arch/i386/kernel/setup.c
--- linux-ac/arch/i386/kernel/setup.c	Wed Aug 15 22:53:09 2001
+++ linux-dj/arch/i386/kernel/setup.c	Wed Aug 15 22:58:03 2001
@@ -1227,13 +1227,13 @@
 				if(mbytes>508)
 					mbytes=508;
 					
-				rdmsr(0xC0000082, l, h);
+				rdmsr(MSR_K6_WHCR, l, h);
 				if ((l&0x0000FFFF)==0) {
 					unsigned long flags;
 					l=(1<<0)|((mbytes/4)<<1);
 					local_irq_save(flags);
 					__asm__ __volatile__ ("wbinvd": : :"memory");
-					wrmsr(0xC0000082, l, h);
+					wrmsr(MSR_K6_WHCR, l, h);
 					local_irq_restore(flags);
 					printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 						mbytes);
@@ -1248,13 +1248,13 @@
 				if(mbytes>4092)
 					mbytes=4092;
 
-				rdmsr(0xC0000082, l, h);
+				rdmsr(MSR_K6_WHCR, l, h);
 				if ((l&0xFFFF0000)==0) {
 					unsigned long flags;
 					l=((mbytes>>2)<<22)|(1<<16);
 					local_irq_save(flags);
 					__asm__ __volatile__ ("wbinvd": : :"memory");
-					wrmsr(0xC0000082, l, h);
+					wrmsr(MSR_K6_WHCR, l, h);
 					local_irq_restore(flags);
 					printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 						mbytes);
@@ -1544,7 +1544,7 @@
 	lo = ~(size-1);		/* Size is a power of 2 so this makes a mask */
 	lo &= ~0xFFF;		/* Remove the ctrl value bits */
 	lo |= key;		/* Attribute we wish to set */
-	wrmsr(reg+0x110, lo, hi);
+	wrmsr(reg+MSR_IDT_MCR0, lo, hi);
 	mtrr_centaur_report_mcr(reg, lo, hi);	/* Tell the mtrr driver */
 }
 
@@ -1700,7 +1700,7 @@
 	 */
 	 
 	for(i=used;i<8;i++)
-		wrmsr(0x110+i, 0, 0);
+		wrmsr(MSR_IDT_MCR0+i, 0, 0);
 }
 
 static void __init winchip2_create_optimal_mcr(void)
@@ -1724,17 +1724,17 @@
 	 *	Mark the registers we are using.
 	 */
 	 
-	rdmsr(0x120, lo, hi);
+	rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
 	for(i=0;i<used;i++)
 		lo|=1<<(9+i);
-	wrmsr(0x120, lo, hi);
+	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
 	
 	/*
 	 *	Wipe unused MCRs
 	 */
 	 
 	for(i=used;i<8;i++)
-		wrmsr(0x110+i, 0, 0);
+		wrmsr(MSR_IDT_MCR0+i, 0, 0);
 }
 
 /*
@@ -1746,20 +1746,20 @@
 	u32 lo, hi;
 	u32 key;
 	
-	rdmsr(0x120, lo, hi);
+	rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
 	lo&=~0x1C0;	/* blank bits 8-6 */
 	key = (lo>>17) & 7;
 	lo |= key<<6;	/* replace with unlock key */
-	wrmsr(0x120, lo, hi);
+	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
 }
 
 static void __init winchip2_protect_mcr(void)
 {
 	u32 lo, hi;
 	
-	rdmsr(0x120, lo, hi);
+	rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
 	lo&=~0x1C0;	/* blank bits 8-6 */
-	wrmsr(0x120, lo, hi);
+	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
 }
 	
 #endif
@@ -1818,7 +1818,7 @@
 				   
 				   Note 0x120 is write only on Winchip 1 */
 				   
-				wrmsr(0x120, 0x01F0001F, 0);
+				wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
 #endif				
 				break;
 			case 8:
@@ -1838,14 +1838,14 @@
 #ifdef CONFIG_X86_OOSTORE
 				winchip2_unprotect_mcr();
 				winchip2_create_optimal_mcr();
-				rdmsr(0x120, lo, hi);
+				rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
 				/* Enable
 					write combining on non-stack, non-string
 					write combining on string, all types
 					weak write ordering 
 				*/
 				lo|=31;				
-				wrmsr(0x120, lo, hi);
+				wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
 				winchip2_protect_mcr();
 #endif
 				break;
@@ -1856,14 +1856,14 @@
 #ifdef CONFIG_X86_OOSTORE
 				winchip2_unprotect_mcr();
 				winchip2_create_optimal_mcr();
-				rdmsr(0x120, lo, hi);
+				rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
 				/* Enable
 					write combining on non-stack, non-string
 					write combining on string, all types
 					weak write ordering 
 				*/
 				lo|=31;				
-				wrmsr(0x120, lo, hi);
+				wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
 				winchip2_protect_mcr();
 #endif
 				break;
@@ -1875,14 +1875,12 @@
 				name="??";
 			}
 
-			/* get FCR  */
-			rdmsr(0x107, lo, hi);
-
+			rdmsr(MSR_IDT_FCR1, lo, hi);
 			newlo=(lo|fcr_set) & (~fcr_clr);
 
 			if (newlo!=lo) {
 				printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo );
-				wrmsr(0x107, newlo, hi );
+				wrmsr(MSR_IDT_FCR1, newlo, hi );
 			} else {
 				printk(KERN_INFO "Centaur FCR is 0x%X\n",lo);
 			}
@@ -1907,9 +1905,9 @@
 		case 6:
 			switch (c->x86_model) {
 				case 6 ... 7:		/* Cyrix III or C3 */
-					rdmsr (0x1107, lo, hi);
+					rdmsr (MSR_VIA_FCR, lo, hi);
 					lo |= (1<<1 | 1<<7);	/* Report CX8 & enable PGE */
-					wrmsr (0x1107, lo, hi);
+					wrmsr (MSR_VIA_FCR, lo, hi);
 
 					set_bit(X86_FEATURE_CX8, &c->x86_capability);
 					set_bit(X86_FEATURE_3DNOW, &c->x86_capability);
@@ -1917,7 +1915,7 @@
 					get_model_name(c);
 					display_cacheinfo(c);
 					
-					rdmsr(0x2A, lo, hi);
+					rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
 					interpret_eblcr(c, lo, 0);
 					break;
 			}
@@ -2165,7 +2163,7 @@
 	if ( c->x86 == 6 && c->x86_model >= 3)
 	{
 		u32 lo, hi;
-		rdmsr(0x2A, lo, hi);
+		rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
 		interpret_eblcr(c, lo, (c->x86_model >= 7) ? 1: 0);	
 	}
 	
@@ -2321,9 +2319,9 @@
 	    disable_x86_serial_nr ) {
 		/* Disable processor serial number */
 		unsigned long lo,hi;
-		rdmsr(0x119,lo,hi);
+		rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
 		lo |= 0x200000;
-		wrmsr(0x119,lo,hi);
+		wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
 		printk(KERN_NOTICE "CPU serial number disabled.\n");
 		clear_bit(X86_FEATURE_PN, &c->x86_capability);
 
diff -urN --exclude-from=/home/davej/.exclude linux-ac/include/asm-i386/msr.h linux-dj/include/asm-i386/msr.h
--- linux-ac/include/asm-i386/msr.h	Wed Aug 15 22:53:19 2001
+++ linux-dj/include/asm-i386/msr.h	Wed Aug 15 23:02:47 2001
@@ -34,19 +34,25 @@
 			  : "c" (counter))
 
 /* symbolic names for some interesting MSRs */
-#define MSR_IA32_PLATFORM_ID		0x017
-
-#define MSR_IA32_APICBASE		0x01b
-#define		MSR_IA32_APICBASE_BSP		(1<<8)
-#define		MSR_IA32_APICBASE_ENABLE	(1<<11)
-#define		MSR_IA32_APICBASE_BASE		(0xfffff<<12)
-
-#define MSR_IA32_UCODE_WRITE		0x079
-#define MSR_IA32_UCODE_REV		0x08b
-
-#define MSR_IA32_PERFCTR0		0x0c1
-#define MSR_IA32_PERFCTR1		0x0c2
+/* Intel defined MSRs. */
+#define MSR_IA32_P5_MC_ADDR		0
+#define MSR_IA32_P5_MC_TYPE		1
+#define MSR_IA32_PLATFORM_ID		0x17
+#define MSR_IA32_EBL_CR_POWERON		0x2a
+ 
+#define MSR_IA32_APICBASE		0x1b
+#define MSR_IA32_APICBASE_BSP		(1<<8)
+#define MSR_IA32_APICBASE_ENABLE	(1<<11)
+#define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
+ 
+#define MSR_IA32_UCODE_WRITE		0x79
+#define MSR_IA32_UCODE_REV		0x8b
+ 
+#define MSR_IA32_PERFCTR0		0xc1
+#define MSR_IA32_PERFCTR1		0xc2
 
+#define MSR_IA32_BBL_CR_CTL		0x119
+ 
 #define MSR_IA32_MCG_CAP		0x179
 #define MSR_IA32_MCG_STATUS		0x17a
 #define MSR_IA32_MCG_CTL		0x17b
@@ -60,14 +66,39 @@
 #define MSR_IA32_LASTINTFROMIP		0x1dd
 #define MSR_IA32_LASTINTTOIP		0x1de
 
-#define MSR_IA32_MC0_BASE		0x400
-#define		MSR_IA32_MC0_CTL_OFFSET		0x0
-#define		MSR_IA32_MC0_STATUS_OFFSET	0x1
-#define		MSR_IA32_MC0_ADDR_OFFSET	0x2
-#define		MSR_IA32_MC0_MISC_OFFSET	0x3
-#define		MSR_IA32_MC0_BANK_COUNT		0x4
-
+#define MSR_IA32_MC0_CTL		0x400
+#define MSR_IA32_MC0_STATUS		0x401
+#define MSR_IA32_MC0_ADDR		0x402
+#define MSR_IA32_MC0_MISC		0x403
+
+/* AMD Defined MSRs */
+#define MSR_K6_EFER			0xC0000080
+#define MSR_K6_STAR			0xC0000081
+#define MSR_K6_WHCR			0xC0000082
+#define MSR_K6_UWCCR			0xC0000085
+#define MSR_K6_PSOR			0xC0000087
+#define MSR_K6_PFIR			0xC0000088
+ 
 #define MSR_K7_EVNTSEL0			0xC0010000
 #define MSR_K7_PERFCTR0			0xC0010004
 
+/* Centaur-Hauls/IDT defined MSRs. */
+#define MSR_IDT_FCR1			0x107
+#define MSR_IDT_FCR2			0x108
+#define MSR_IDT_FCR3			0x109
+#define MSR_IDT_FCR4			0x10a
+
+#define MSR_IDT_MCR0			0x110
+#define MSR_IDT_MCR1			0x111
+#define MSR_IDT_MCR2			0x112
+#define MSR_IDT_MCR3			0x113
+#define MSR_IDT_MCR4			0x114
+#define MSR_IDT_MCR5			0x115
+#define MSR_IDT_MCR6			0x116
+#define MSR_IDT_MCR7			0x117
+#define MSR_IDT_MCR_CTRL		0x120
+
+/* VIA Cyrix defined MSRs*/
+#define MSR_VIA_FCR			0x1107
+ 
 #endif /* __ASM_MSR_H */